Semiconductor Fabrication

From raw silicon to tested die · 41 steps · 11 chokepoints

▸ 1

Mine Quartz

mine

HIGH

High-purity quartz from Spruce Pine NC (70-80% global supply). Also Sibelco, Jiangsu Pacific Quartz.

Semiconductor-Grade Quartz

Suppliers 2 (Sibelco + The Quartz Corp) Scenario Hurricane Helene (Sep 26, 2024) dumped 2+ feet of rain. Both mines shut, CSX rail line damaged. CNN: "Devastation could bring semiconductor chipmaking to a halt." Sibelco restarted in 14 days. The scare was real but the near-miss exposed how one weather event in one small town cascades globally. The quartz makes crucibles for the Czochralski process (pulling silicon ingots at 1,400C). At those temperatures, impurities migrate from crucible walls into silicon even through coatings. 9N purity silicon demands near-perfect quartz. Secondary deposits in Norway and Brazil cannot match Spruce Pine. Downstream All silicon wafer makers (Shin-Etsu, SUMCO, GlobalWafers, Siltronic, SK Siltron), then the entire semiconductor chain. Geography Spruce Pine, North Carolina (population ~2,000). 70-90% of world's high-purity quartz. Deposit formed 380 million years ago when magma cooled in the absence of water over 100 million years, producing quartz purity found essentially nowhere else on Earth.

▸ 2

Reduce to Metallurgical Si

reduce

Electric arc furnace at 2000C. 98-99% pure MGS. China ~70% of production.

▸ 3

Purify to Polysilicon

purify

Siemens process: trichlorosilane distillation to 9N-11N purity. Most energy-intensive step (100-200 kWh/kg). Solar uses 90%, chips 10% but highest purity.

▸ 4

Grow Single Crystal Ingot

grow

Czochralski method: 1425C melt, seed pull over 24-72hrs. 300mm diameter, 200-300kg. Any vibration/impurity = defects. Float Zone alternative for power devices.

▸ 5

Slice into Wafers

slice

Diamond wire saw, lapping, etching, CMP to <0.5nm RMS. Epitaxial layer optional.

▸ 6

Wafer Enters Fab

enter_fab

CRITICAL

Wafer enters cleanroom. 2-3 months, 50-100 layer cycles ahead.

Leading-Edge Foundry

Suppliers 1 (TSMC ~90% of <7nm) Scenario This is the single largest concentration of economic value in one company in human history. TSMC manufactures ~90% of the world's most advanced chips. A Taiwan crisis does not just halt chips, it halts the global economy: smartphones, AI infrastructure, automotive, defense, medical devices, telecommunications. No other foundry can absorb even a fraction of TSMC's volume. Samsung Foundry and Intel are years behind at leading edge. Arizona, Japan (JASM), and Germany (ESMC) fabs together represent less than 5% of TSMC's total capacity. Downstream Apple, NVIDIA, AMD, Qualcomm, Broadcom, MediaTek, every hyperscaler, every smartphone, every AI training cluster. Geography Taiwan (Hsinchu, Tainan, Kaohsiung). Arizona fabs under construction but mass production years away. TSMC processes Apple, NVIDIA, AMD, Qualcomm, Broadcom, and nearly every advanced chip design on Earth.

▸ 7

Deposit Thin Film

deposit

HIGH

Grow or deposit oxide/nitride/metal/high-k on wafer. Multiple methods with distinct equipment and suppliers.

High-Pressure Annealing (HPSP)

Suppliers 1.5 (HPSP ~85-90%, YEST emerging 2025) Scenario At every interface between silicon and its oxide, dangling bonds trap charge carriers, causing transistor instability and leakage. HPA forces hydrogen/deuterium at 10-30 atmospheres into the device, passivating these traps. The Si-D bond (deuterium) is 10x more resistant to degradation than Si-H, a "giant isotope effect." As transistors shrink to GAA, surface area (and dangling bonds) increases dramatically while thermal budgets tighten. You cannot use >900C annealing anymore. Pressure replaces temperature. The catch: high-pressure hydrogen means one mistake causes an explosion. Massive regulatory barrier to entry. YEST is developing competing equipment (30 HPSP patents, ongoing lawsuit). Downstream TSMC (exclusive), Samsung, SK Hynix, Micron. Every advanced logic and memory node requires interface passivation. Geography Korea. Called "Korea's ASML" by Korean media. Revenue grew from 24B won (2018) to 1.79T won (2023), 53% operating margin. Carlyle, Blackstone, KKR, Bain, MBK all bid for a 40.9% controlling stake (~$1.5B). TSMC is exclusive customer (~50-60% of revenue).

▸

CVD / PECVD

dep_cvd

Chemical Vapor Deposition. PECVD for low-temp films. Workhorse for oxide, nitride, polysilicon.

▸

HDPCVD (high-aspect-ratio)

dep_hdpcvd

High Density Plasma CVD: simultaneous dep+etch prevents pinch-off voids in sub-0.8um features. Critical for 3D NAND and advanced logic gap-fill.

▸

ALD (atomic precision)

dep_ald

Atomic Layer Deposition: self-limiting surface reactions for angstrom-level control. Essential for high-k gates, Mo deposition, barrier layers. ASM International leads.

▸

PVD / Sputtering

dep_pvd

Physical Vapor Deposition for metal films (Cu seed, barrier metals, interconnect). Applied Materials Endura platform dominates.

▸ 8

Coat with Photoresist

coat

Spin-coat resist, soft-bake. 5 Japanese companies control ~90%. Chemically amplified resists (CAR) with photoacid generators.

▸ 9

Lithography (Expose)

litho

Pattern transfer through photomask onto resist. Resolution depends on wavelength.

▸

DUV (ArF immersion)

litho_duv

ArF 193nm through water, effective 134nm. Enabled 45nm to 7nm. ASML 80%+, Nikon and Canon compete for mature nodes.

▸

EUV (13.5nm)

litho_euv

CRITICALCRITICALCRITICALHIGHHIGH

Extreme UV: tin droplet laser plasma source, Bragg mirror optics in vacuum. ASML monopoly. $380M+ per tool, ~50/year. 7nm and below.

EUV Lithography Scanners

Suppliers 1 (ASML) Scenario Each machine weighs 180 tons, ships in 40 freight containers and 3 Boeing 747s, takes 250 engineers 6 months to install. Only ~220 EUV systems exist worldwide. A Jan 2022 fire at ASML's Berlin factory (wafer clamps, reticle chucks) nearly disrupted output. 12-18 month lead times mean a Veldhoven disruption wouldn't stop existing fabs, but no new capacity could come online. China's reverse-engineering attempt (secret Shenzhen lab, ~100 engineers) has not produced a single chip. Downstream Every sub-7nm chip on Earth. Apple, NVIDIA, AMD, Qualcomm, all hyperscalers. A single EUV machine enables ~$5-10B/yr in chip revenue. Geography Netherlands (Veldhoven, population 45,000). One campus, 20,000+ employees, 75,000 m2 cleanroom. Sub-tier: Zeiss (DE optics), TRUMPF (DE laser), 5,150+ suppliers across multiple countries.

EUV Laser Source

Suppliers 1 (TRUMPF) Scenario The most powerful industrial laser ever mass-produced. Fires 50,000 tin droplets/second, each vaporized into plasma at 220,000C (40x hotter than the sun's surface) to emit 13.5nm EUV light. German intelligence investigated after Huawei targeted TRUMPF employees with 3x salary offers for CO2 laser amplifier expertise. In 2017, TRUMPF acquired Access Laser (US) to eliminate a potential second source. Downstream ASML cannot ship a single EUV machine without TRUMPF. Cascade: TRUMPF -> ASML -> every advanced foundry -> every fabless company -> every AI chip, smartphone, and server. Geography Germany (Ditzingen). Family-owned (Leibinger-Kammuller). EUR 70M dedicated factory, 10 production bays, 10-week assembly per unit. Perhaps a few hundred people worldwide know how to build these.

EUV Optics

Suppliers 1 (Carl Zeiss SMT) Scenario The mirror system is 1.5m tall, weighs 3.5 tons, and contains 35,000+ parts. If scaled to the size of Germany, the highest bump on the surface would be 0.1mm. Zeiss uses ion beam figuring to knock off individual molecules. These tolerances took 20+ years to achieve and no one else is close. Downstream Same cascade as TRUMPF: no Zeiss mirrors means no EUV scanners means no advanced chips. Geography Germany (Oberkochen). ASML owns 24.9% of Zeiss SMT (invested EUR 1.5B). Exclusive supplier relationship.

EUV Pellicles

Suppliers 2 (ASML in-house ~60-70%, S&S Tech ~20-30%) Scenario Samsung has never used EUV pellicles in production. They have been running without them, accepting higher defect risk. Their Taylor TX fab (2026) will be Samsung's first to use pellicles, ordered 25B won ($17.5M) in equipment for it. At 2nm, running pellicle-free is no longer viable because a single particle on a critical EUV layer can ruin every chip on a wafer. Carbon nanotube pellicles (Canatu/imec) achieve 97% transmission and stability above 1,500C, the path forward for High-NA EUV. Downstream All EUV production. Without pellicles, immediate yield degradation. At 2nm nodes, pellicles are mandatory. Geography Netherlands (ASML) + Korea (S&S Tech, 91% transmittance). The problem: 13.5nm EUV light is absorbed by almost all materials. The membrane must transmit >90% of EUV, survive 600W+ source power, and be freestanding over 110x140mm.

EUV Reticle Pods

Suppliers 1 (Gudeng Precision ~80%+) Scenario In 2012, Gudeng designed the first commercial EUV pod using PEEK-ESD material with lower contamination and tighter ESD tolerance than incumbents. EUV reticles cost millions and a few nanometers of particle contamination can ruin entire wafer lots. Gudeng's pods simply kept masks cleaner. TSMC validated them and never looked back. Now building a factory in Japan and collaborating with ASML on High-NA pods. Neither the $24B American contamination giant nor ASML itself could displace a 379-person company in a Taipei suburb. Downstream All EUV production. Masks need fresh pods continuously. Days-to-weeks buffer. Geography Taiwan (Tucheng, New Taipei City). 379 employees. Sole EUV pod supplier to TSMC. Entegris ($3.5B+ revenue) fought a patent war, won NT$978M ($32.6M) in Taiwan's highest-ever patent damages (2019), then settled and licensed TO Gudeng (2020), acknowledging they lost the market.

▸

NIL (nanoimprint, emerging)

litho_nil

LOW

Canon FPA-1200NZ2C: stamps mask pattern into resist. 5nm-equiv at ~1/10th EUV cost/power. Under evaluation at TIE (Intel, Samsung, NXP). Potential EUV alternative for memory.

Nanoimprint Lithography

Suppliers 1 (Canon) Scenario NIL works by pressing a quartz template into resist, like a stamp. The fundamental problem is physical contact: templates wear out, particles transfer defects immediately, and throughput is limited by resist curing time. Kioxia is the most active evaluator (testing for 3D NAND). Canon targets 2028 for NAND templates. If NIL succeeds, the bottleneck shifts from ASML scanners to template makers. DNP (Dai Nippon Printing) is targeting 2027 mass production of 1.4nm-capable nanoimprint templates, creating a potential new chokepoint. Downstream Memory makers (Samsung, SK Hynix, Kioxia). Samsung's Taylor TX fab reportedly plans 2026 risk production but not confirmed for high-volume. Geography Japan. Canon shipped first FPA-1200NZ2C to Texas Institute for Electronics in Sep 2024. Patterns at 14nm. No foundry has committed to high-volume manufacturing yet.

▸ 10

Develop

develop

Chemical developer dissolves exposed (positive) or unexposed (negative) resist.

▸ 11

Etch the Pattern

etch

Plasma or wet etch removes material where resist cleared. Selectivity and aspect ratio are key challenges.

▸

Dielectric Etch

etch_diel

Oxide, nitride, low-k etch. Lam Flex, TEL Tactras, Applied Centura.

▸

Conductor Etch

etch_cond

Poly-Si gates, metal interconnects. Lam Kiyo dominates. TEL Tactras.

▸

Atomic Layer Etch

etch_ale

Self-limiting removal, atomic precision. Critical for FinFET/GAA gate formation. Lam, TEL lead.

▸ 12

Ion Implant (Dope)

implant

Accelerate dopant ions (B, P, As) into wafer. Controls transistor threshold voltage. Repeats dozens of times per chip.

▸ 13

Strip Resist & Clean

strip

O2 plasma ash or solvent strip. SC-1, SC-2, HF clean sequences. SCREEN and TEL equipment.

▸ 14

CMP (Planarize)

cmp

Chemical-mechanical polishing. Enables multi-layer chips. Now also enables hybrid bonding (angstrom flatness) and handles SiC/GaN extreme hardness.

▸

FEOL CMP (logic, 3D NAND)

cmp_feol

Front-end-of-line: oxide/nitride polish for transistor layers. 40:1 selectivity with amino acid chemistries.

▸

BEOL CMP (Cu interconnect)

cmp_beol

Back-end-of-line: copper damascene polish. DuPont pads dominate. Mo-specific slurries emerging.

▸

Hybrid Bonding CMP

cmp_bond

Angstrom-level flatness for direct Cu-to-Cu bonding in 3D integration. Enables HBM4, chiplet stacking. Most demanding CMP application.

▸ 15

Inspect & Measure

inspect

Feature dimensions, alignment, defect scanning. Shifting from offline to continuous AI-driven inline monitoring.

▸

Defect Inspection

insp_defect

Find particles, pattern defects. KLA 39xx/29xx dominates. Applied SEMVision review.

▸

Overlay Metrology

insp_overlay

Layer-to-layer alignment. ASML YieldStar, KLA Archer.

▸

CD Metrology

insp_cd

Critical dimension measurement. Hitachi CD-SEM leads. OCD scatterometry.

▸

In-situ / AI Process Control

insp_insitu

Real-time sensor data (MFCs, plasma monitors, optical) feeds AI for predictive yield management. Horiba sensors, MKS MFCs. PDF Solutions, Tignis software.

▸ 16

Wafer Probe Test

probe

HIGH

Probe card needles contact each die. ATE runs test vectors. Failed dies mapped. Yield = % working.

Probe Cards (esp. HBM)

Suppliers 2 (FormFactor ~35-40%, Technoprobe ~25-30%) Scenario The yield math is brutal: if individual die yield is 95%, a 12-die HBM stack yields just 54% (0.95^12). At 99% die yield, stacks yield 89%. Every fraction matters, making pre-stack testing essential. Each HBM die has ~4,000 microbumps at 55um pitch, needing 100,000+ simultaneous contact points generating 300+ kg reaction force. Probes must maintain stable alignment as temperatures swing at 9.6 GT/s data rates. HBM is the most test-intensive component in an AI server. Downstream All wafer production needs probe cards. HBM especially concentrated. Probe card shortage directly constrains HBM output, which constrains AI GPU availability. Geography US (FormFactor) + Italy (Technoprobe, Cernusco Lombardone near Milan). Founder Giuseppe Crippa started making probe cards in his garage in 1989 at age 54 after retiring from STMicroelectronics. When Technoprobe IPO'd in 2022, the family became billionaires ($4B stake). Crippa passed away July 2025.

▸ 17

Dice into Chips

dice

Backgrind to 50-100um, diamond blade or laser dice. Disco 70%+ share.

▸ 18

Package the Chip

package

Die into protective package with external connections. Fastest-growing strategic segment.

▸

Wire Bond / Flip Chip

pkg_trad

Traditional: wire bond + mold. Flip chip: bumps directly to substrate. Still majority of production.

▸

Fan-out (InFO, eWLB)

pkg_fanout

TSMC InFO for Apple SoCs. Wafer-level redistribution. Lower cost than interposer.

▸

2.5D Interposer (CoWoS)

pkg_25d

CRITICAL

Dies on silicon interposer with TSVs. TSMC CoWoS dominates AI chips (GPU + HBM). The AI packaging bottleneck.

CoWoS Advanced Packaging

Suppliers 1 (TSMC ~90%) Scenario The real problem is physics: tiling GPU chiplets, silicon bridges, and an interposer onto a substrate means materials that expand at different rates when heated. This caused warping in NVIDIA Blackwell B100/B200 GPUs, forcing a top-metal redesign. Once the interposer exceeds the reticle boundary (~26x33mm), yield and fragility spike. Capacity went from 35K wafers/month (late 2024) to 75K (2025) to a target of 130K by end 2026, and it is still sold out. Jensen Huang: capacity "quadrupled in under two years" and remained a bottleneck. Downstream NVIDIA, AMD, Google TPU, Amazon Trainium, Microsoft Maia. A single CoWoS package costs $1,000-3,000+ and enables a $25,000-40,000+ AI accelerator. Geography Taiwan (Chiayi AP7 plant, 8 new fabs under development). Arizona packaging plants not expected until 2028. NVIDIA books 800,000+ wafers/yr, taking over half of all CoWoS capacity.

▸

3D / Hybrid Bonding

pkg_3d

Direct die stacking. Cu-to-Cu hybrid bonding at <10um pitch. HBM stacks 8-16 DRAM dies. Enables chiplet architectures.

▸

Co-packaged Optics

pkg_cpo

Optical engines integrated with ASICs via TSMC COUPE platform. NVIDIA Spectrum-X, Broadcom Bailly. Replaces copper for scale-up AI networking. Market >$20B by 2036.

▸ 19

Final Test & Burn-in

final_test

Test at operating speed/temp. Burn-in screens early failures. Speed binning sorts by performance.

PCB Manufacturing

Printed circuit board fabrication — converges at board assembly · 9 steps

▸ 1

PCB Design & Layout

pcb_design

Impedance-controlled routing, signal integrity simulation. Top 4 hold ~92%: Siemens/Mentor (Xpedition), Cadence (Allegro), Altium, Zuken (CR-8000, dominant in Japan). 20-60+ layer server boards require months of design.

▸ 2

Core & Prepreg Lamination

pcb_laminate

Copper-clad laminates (CCL). Kingboard (#1 global), Shengyi (#2). High-frequency: Panasonic Megtron (server/AI dominant), Rogers (RF/5G), Isola. Doosan (monopoly on NVIDIA Blackwell server trays). Nan Ya, ITEQ, Taiwan EMC.

▸ 3

Inner Layer Imaging & Etch

pcb_inner

LDI (laser direct imaging) replacing film exposure. Orbotech/KLA (32-40% LDI share), SCREEN (#2, ~21%). Dry film photoresist: Asahi Kasei, Hitachi Chemical/Resonac, DuPont hold ~80% combined.

▸ 4

Multi-layer Lamination

pcb_stackup

Stack prepreg + etched cores under heat and pressure. 4 layers (consumer) to 60+ layers (server/networking). Equipment: Lauffer, Burkle (Germany), Kitagawa Seiki (Japan). Small niche market (~$53M).

▸ 5

Via Drilling

pcb_drill

Mechanical: Schmoll (Germany, leading), Via Mechanics (Japan), Hitachi High-Tech. Laser: Mitsubishi Electric, ESI/MKS. Han's Laser (30%+ of China market). HDI boards need multiple drill cycles.

▸ 6

Copper Plating

pcb_plate

Top 4 control >60% of ~$2.5B market. Atotech/MKS (#1, ~22%), MacDermid Alpha/Element Solutions, DuPont, JCU (Japan). Surface finish chemistry: Uyemura (>40% ENEPIG). Via fill plating critical for HDI.

▸ 7

Outer Layer Processing

pcb_outer

Pattern, plate, etch outer copper traces. mSAP for <30um line/space (IC substrates). Chemistry: MacDermid Alpha, Atotech. Same LDI and plating equipment as inner layer but tighter specs. AT&S pioneer in mSAP.

▸ 8

Solder Mask & Surface Finish

pcb_finish

Solder mask: Taiyo Ink/Taiyo Holdings >50% global share (dominant). Hitachi Chemical/Resonac #2. Surface finish (ENIG/ENEPIG/OSP): Atotech, MacDermid Alpha, Uyemura, JCU.

▸ 9

Electrical Test & Inspection

pcb_test

Flying probe: atg Luther & Maelzer/Mycronic (leading), Takaya (Japan, invented it 1987), SPEA (Italy). AOI: Orbotech/KLA (~70% bare board AOI), Koh Young (#1 in 3D SPI, 16 consecutive years). Camtek, Omron.

Optics & Photonics

Optical components and modules — converges at packaging · 6 steps · 3 chokepoints

▸ 1

Silicon Photonics Fabrication

opt_sipho

Waveguides, ring modulators, Ge photodetectors on SOI wafers. Modified CMOS at foundries: TSMC (COUPE), GlobalFoundries (Fotonix), Tower Semi (300mm), STMicroelectronics (PIC100, Crolles). Intel internal SiPho fab.

▸ 2

III-V Laser & Amplifier Fab

opt_iiiv

HIGHHIGHHIGH

InP/GaAs epitaxial growth (MOCVD/MBE). EML: Mitsubishi Electric (~50% EML chips), Lumentum, Coherent, Sumitomo Electric. VCSEL: Coherent (41%) + Lumentum (37%) = ~78%. CW lasers: Broadcom, MACOM. NVIDIA pre-allocated EML capacity past 2027.

EML Lasers (III-V)

Suppliers 1 (Lumentum leads 200G/lane) Scenario Copper interconnects physically cannot handle 800 Gbps speeds AI clusters require. The transition from electrical to optical is not optional, it is physics. Each link needs indium phosphide (InP) EML laser chips. Global InP capacity is severely constrained. Coherent CEO warned the industry would be "constrained through 2027." Lumentum is undershipping by 25-30%. NVIDIA pre-allocated capacity, effectively locking out competitors. Downstream NVIDIA, Broadcom CPO switches, every hyperscaler building AI clusters. Without optical interconnects, AI scale-up networks stay copper-limited. Geography US (Lumentum). In March 2026, NVIDIA invested $2B in Lumentum plus $2B in Coherent, a $4B bet on optics. Lumentum building 240K sq ft InP laser fab in Greensboro NC, production mid-2028.

InP Substrates

Suppliers 5 (AXT/Tongmei ~35%, Sumitomo ~30%, JX ~15%, Freiberger ~10%, InPact ~5%) Scenario 70% supply-demand gap: ~2M pieces demanded in 2025 against ~600K capacity. InP is the substrate for every EML laser chip in every AI optical link. Indium itself is exclusively a zinc mining byproduct (like hafnium from nuclear Zr), with China controlling 65% of production. Korea Zinc (#1 non-Chinese producer) is building a $7.4B US smelter. Growing InP crystals is extremely difficult: the material is brittle, toxic (phosphine gas), and requires defect-free single crystals. Expanding capacity takes 18-24 months per MOCVD reactor. Downstream Every EML laser maker (Lumentum, Coherent, Mitsubishi, Broadcom, Sumitomo). Cascades to all 800G/1.6T optical transceivers, then to all AI cluster networking. Geography China (AXT/Tongmei Beijing, 35% share, export controls Feb 2025 requiring 60-day permits per order), Japan (Sumitomo, JX), Germany (Freiberger), France (InPact). Industry shifting from 3-inch to 6-inch wafers (4x more laser dies, 60% lower cost/die).

AI Optical Module Assembly

Suppliers ~10 (Innolight ~40%, Eoptolink ~20%, Coherent, Broadcom, others) Scenario If export controls tighten on Chinese optical module makers, there is no Western capacity to absorb the volume. This is the optical equivalent of the TSMC concentration risk but in reverse: Western AI infrastructure depends on Chinese assembly. Fabrinet (Thailand) is the largest non-Chinese contract manufacturer but at $3.4B revenue cannot replace Innolight's $5.3B alone. The irony: Chinese module makers depend on US/Japanese laser chips, while US AI clusters depend on Chinese module assembly. Downstream NVIDIA (directly), Microsoft, Amazon, Google, Meta. Every AI training cluster and hyperscaler network fabric. Geography China: 7 of top 10 transceiver companies are Chinese. Innolight (Suzhou) + Eoptolink = 60% of NVIDIA's 800G orders. Pentagon recommended both for Section 1260H Chinese military-linked list (Oct 2025). Both depend on Western EML chips (Lumentum, Coherent, Mitsubishi) and DSP chips (Marvell, Broadcom).

▸ 3

Optical Fiber & Cable

opt_fiber

Preform fabrication (OVD/MCVD), fiber drawing at ~2000C, UV coating, cabling. Top 5: Corning, Prysmian, Sumitomo Electric, Furukawa, YOFC. China: YOFC (#1 preform, 30% global), Hengtong, ZTT, FiberHome.

▸ 4

Passive Optical Components

opt_passive

Lenses, thin-film filters, AWG mux/demux, isolators, WSS modules. Coherent, Lumentum, Santec (WSS). Furukawa/Proterial (>50% global ITLA share). China: O-Net Technologies, Accelink.

▸ 5

Optical Transceiver Assembly

opt_module

Laser + PD + driver IC + TIA into pluggable module. 400G/800G/1.6T. Zhongji Innolight #1 globally (~30%, ~40% of 800G). Coherent #2, Eoptolink #3 (179% YoY growth). Chinese makers hold 7 of top 10 and ~60% of 800G market.

▸ 6

Optical Test & Qualification

opt_test

BER testing, eye diagrams, insertion loss, spectral analysis. Keysight + VIAVI (~30% of $1.7B market). Anritsu, EXFO, Yokogawa (AQ6370E won ECOC 2024 award). SiPho/CPO test growing to $2B+ by 2032.

System Integration

Where semiconductor, PCB, and optical paths converge · 2 steps

▸ 1

Board Assembly

assemble

SMT pick-and-place onto PCBs. 50,000+ components/hour.

▸ 2

Product Ships

ship

Finished products: GPUs, mobile SoCs, memory modules, AI accelerators, automotive chips.

Materials & Supply Chain

Cross-cutting materials, chemicals, and components · 14 steps · 16 chokepoints

▸ 1

Photoresists

mat_resist

CRITICAL

5 Japanese companies hold ~90%. ArF, EUV, KrF resists. CAR chemistry with photoacid generators.

Advanced Photoresists

Suppliers 5 (all Japanese) Scenario In July 2019, Japan restricted photoresist exports to Korea over a wartime labor dispute. SK Hynix cut NAND production 15%. Korea's Japanese resist dependency dropped from 93.2% to 65.4% by 2024, partly by importing from JSR's Belgium subsidiary. But for EUV resist, Japan still dominates. The chemistry barrier is fundamental: EUV photons carry 14x more energy than DUV, so fewer hit each pixel, creating statistical noise (shot noise) that blurs features. Solving this requires decades of iterative formulation that no one else has. Fabs hold 2-4 weeks of resist inventory. Shelf life is limited. Downstream All fabs at advanced nodes. A few hundred dollars of resist per wafer enables $10,000-50,000+ of finished chips. Geography Japan: JSR, TOK, Shin-Etsu, Fujifilm, Sumitomo. For metal-oxide EUV resist (the cutting edge), Japanese companies control ~97%.

▸ 2

CMP Slurries & Pads

mat_cmp

HIGHHIGH

DuPont pads dominate. Entegris (Cabot), Merck, Fujifilm, Resonac slurries. Mo-specific chemistries emerging.

CMP Polishing Pads

Suppliers 1 (DuPont ~79%) Scenario Fabs optimized their entire CMP process around IC1000. Switching pads means requalifying every CMP recipe at every node, an enormously expensive and risky proposition. That is why 79% market share has not budged. In Apr 2025, China's SAMR opened an antitrust investigation into DuPont, shares plunged 12.75% in one day. Widely seen as retaliatory leverage given the CMP pad monopoly. Later suspended. Every advanced wafer undergoes 20-30+ CMP steps. Downstream All fabs globally. Every single wafer at every node. Geography US (DuPont/Qnity). In 1968, William Budinger (ex-DuPont) founded Rodel in Delaware to remove dust from printing presses. IBM asked: can you flatten a semiconductor wafer? The IC1000 pad became the industry standard in the 1990s and the formulation has not changed in 20+ years. The product has survived four corporate name changes (Rodel -> Rohm and Haas -> Dow -> DowDuPont -> Qnity).

CMP Slurries (esp. tungsten)

Suppliers 3 (Entegris/CMC ~35-40%, Fujimi ~15-20%, Merck ~10-15%) Scenario Qualification takes 12-18 months because changing slurry affects removal rate, selectivity, uniformity, dishing, erosion, and defectivity simultaneously. A slurry change can alter topography in ways that only show up as yield loss steps later in the process. 80% of CMP yield excursions trace to three causes: particle count spikes in incoming slurry, pH excursions causing abrasive agglomeration, and storage anomalies. At advanced nodes, a single 20nm scratch kills a die. Every advanced wafer undergoes 20-30+ CMP steps. Shelf life varies (weeks to months). Fabs hold 2-4 weeks of safety stock. Downstream All fabs at all nodes. CMP consumables cost $50-200+ per wafer. A CMP excursion can scrap an entire lot ($500K-2M+). Geography US (Entegris dominant in W slurry ~50-60%) + Japan (Fujimi) + Germany (Merck). Each slurry is a precise chemistry: abrasive particle size distribution, pH, oxidizer, corrosion inhibitor, and surfactant, all co-optimized for a specific fab's tool, film stack, and pattern density.

▸ 3

Bulk & Specialty Gases

mat_gas

HIGHCRITICAL

Bulk: N2, O2, Ar, H2, He. Specialty: NF3, WF6, SiH4. Rare: Ne, Kr, Xe. He critical for wafer cooling, leak detection, and EUV source purge. On-site generation (bulk) or delivered (specialty/rare).

Semiconductor-Grade Neon

Suppliers 3+ (diversified post-2022 but tight capacity) Scenario Feb 24, 2022: Cryoin halted operations the day Russia invaded. Ingas in Mariupol was besieged, the city effectively destroyed. Combined output (25,000-35,000 m3/month, 75% going to chipmakers) went to zero overnight. Chinese neon prices surged 10x in March 2022. Fabs survived because TSMC, Samsung, Intel had 3-6 months of strategic reserves. The gas mix in ArF excimer lasers is >95% neon, ~3-4% argon, <1% fluorine. Testing showed replacing 60% of neon with helium cut pulse energy 60%. There is no substitute. DUV is still used for the majority of layers even at EUV nodes. Downstream Every fab on Earth using DUV lithography (which is every fab). Geography Pre-2022: Two Ukrainian companies (Ingas in Mariupol, Cryoin in Odessa) inherited Soviet steel mill purification infrastructure and supplied 45-54% of global semiconductor neon. Post-2022: diversified to US/EU/Korea/China at higher cost.

Semiconductor-Grade Helium

Suppliers 3 gas majors (Linde 30% Qatar He-2, Air Products operates QH2, Air Liquide 50% Ras Laffan). US ~42% global production. Russia Amur delayed. Scenario No substitute. Fabs must curtail production as buffer stocks deplete. Samsung/SK Hynix claim 6mo stockpile but Fitch estimates 6-week cliff before allocation tightening. DRAM/HBM prices already nearly doubled Q1 2026. Micron warned H2 2026 wafer starts at risk. EUV cooling, leak detection, wafer backside cooling all require helium. Per-wafer He consumption increases at advanced nodes. Demand projected 5x by 2035. Downstream Korea most exposed (64.7% He from Qatar). Samsung + SK Hynix = 70% DRAM, 80% HBM. Taiwan also Qatar-dependent (TSMC monitoring). Japan better buffered (70% fab recycling at 80-90% recovery, METI 20B yen program, Iwatani dual-sourcing ~50% domestic share). All EUV fabs at risk. Geography Qatar Ras Laffan OFFLINE since Mar 2 2026 (3-5yr repair for damaged LNG trains). Strait of Hormuz blockaded (tanker traffic -70%). US largest producer (81M m³/yr). Helium output permanently cut 14% even after partial Qatar recovery. Spot prices doubled to $1,000-1,200/MCF.

▸ 4

Wet Chemicals & UPW

mat_chem

H2SO4, H2O2, NH4OH, HCl, HF, HNO3. Stella Chemifa for high-purity HF. Ultra-pure water systems.

▸ 5

Photomasks

mat_masks

CRITICALHIGHHIGH

60-100 masks per 3nm chip ($15-20M set). E-beam written, optically inspected. EUV blanks from Hoya, AGC.

EUV Mask Inspection

Suppliers 1 (Lasertec) Scenario A buried phase defect of 0.3nm (a single atom) deforms 40+ overlying layers and prints errors on every die. Only Lasertec's ACTIS tools can detect these at EUV wavelength. Without them, mask shops ship defective masks and fabs discover the problem only after printing millions of defective chips. There is no workaround: DUV-based inspection cannot see EUV-specific multilayer phase defects. Downstream Every EUV mask shop, every EUV-node fab. Yield collapses without actinic inspection. Geography Japan (Yokohama). Only company making actinic (at-wavelength) EUV mask inspection tools. Since EUV masks are reflective multilayer mirrors, defects invisible to conventional inspection only reveal themselves under actual 13.5nm light.

Photomask Blanks

Suppliers 2 (Hoya ~75% EUV, AGC ~25%) Scenario An EUV blank is a $100,000+ mirror: 40-50 alternating layers of molybdenum and silicon, each ~3nm thick, forming a Bragg reflector tuned to 13.5nm light. The substrate is polished to sub-molecular flatness. A defect of 0.3nm height (a single atom) deforms all 40+ overlying layers, disrupting the Bragg condition and printing errors on every die exposed through that mask. The defect tolerance is effectively zero. Lead times 8-16 weeks. Downstream All mask shops (Photronics, DNP, Toppan, Taiwan Mask). A single EUV mask costs $300K-500K. A full mask set for an advanced SoC exceeds $10-20M. Each mask exposes thousands of wafers worth billions. Geography Japan. The same Hoya that makes contact lenses and medical endoscopes holds 75%+ of EUV photomask blanks. AGC (Asahi Glass) is the only other supplier.

E-beam Mask Writers

Suppliers 1 (NuFlare ~85% single-beam, IMS 81.5% multi-beam) Scenario NuFlare's MBM-2000PLUS uses 262,144 programmable beams (10nm each) and writes one EUV mask in ~8.7 hours. One mask. A 3nm chip needs 70-100 masks. A full EUV mask set costs $30-40M. Only ~10-12 mask writers ship industry-wide per year. Mask shops have been reluctant to invest in spare capacity, so when demand spikes there is no slack. KLA's IMS Nanofabrication (Austrian origin) now leads multi-beam revenue (81.5% in 2024), creating a second chokepoint. Downstream All mask shops, then all fabs. No new mask sets means no new chip designs enter production. Expanding mask capacity takes 1-2 years. Geography Japan. NuFlare is a subsidiary of Shibaura Machine (formerly Toshiba Machine), not separately listed. Every advanced photomask in the world was likely patterned on a NuFlare tool.

▸ 6

EDA Software & IP

mat_eda

CRITICALHIGH

Synopsys + Cadence duopoly for design tools. ARM for CPU architectures. Rambus for memory interface IP.

EDA Tools

Suppliers 3 (Synopsys ~33%, Cadence ~30%, Siemens EDA ~16%) Scenario Pirating EDA is not like pirating Photoshop. The tools are synchronized with foundry PDKs and process updates. Using an old cracked version means designs are out of sync with the fab and verification fails. China's leading domestic alternative (Empyrean, revenue ~$168M, added to Entity List Dec 2024) works at 7nm+ but cannot support GAA/CFET architectures. Without current EDA tools, chip design at advanced nodes effectively stops. Downstream Every semiconductor design company on Earth. China's chip industry most directly affected by export controls. Geography US (Synopsys $6.1B, Cadence $4.6B) + Germany/US (Siemens EDA). Together hold ~80% of China's EDA market. Already weaponized: GAAFET EDA ban Aug 2022, full licensing requirement May 2025 (rescinded 6 weeks later after China retaliated with rare earth restrictions).

Embedded NVM IP (eMemory)

Suppliers 1 (eMemory ~70-80%) Scenario When you design a chip at TSMC and need one-time-programmable memory for calibration data, encryption keys, or chip ID, the IP block in TSMC's PDK (Process Design Kit) is eMemory's NeoFuse. Qualified across N7 through N4P and beyond. If eMemory were disrupted, new chip designs at TSMC could not tape out with OTP/PUF functionality. Existing production continues but new designs are blocked. A company most chip designers have never heard of. Downstream All new chip designs at TSMC, Samsung Foundry, UMC, GlobalFoundries. Billions of chips pay eMemory royalties. Geography Taiwan. $6B market cap on just $117M revenue. 770+ silicon IPs deployed on TSMC processes. Won TSMC "OIP Partner of the Year" 15 consecutive years. Revenue is almost entirely royalties, a toll booth embedded in the world's most important foundry.

▸ 7

Interconnect Metals (Cu, W, Mo)

mat_metals

HIGH

Cu damascene (mainstream), W (contacts), Mo (emerging at 2nm+: barrierless, lower scaled resistance). MoO2Cl2 solid precursors need heated delivery. Ru also evaluated.

Molybdenum Precursors

Suppliers 2-3 (Entegris leads, Air Liquide, Merck) Scenario Below ~7nm wire width, copper's resistivity explodes (electron mean free path ~39nm). Molybdenum's EMFP is 11.2nm, so it stays low until much smaller dimensions. Mo also needs no barrier/liner layer, reducing resistance ~56% vs barrier-lined tungsten. The catch: Mo precursors (MoCl5, MoOCl4) are solids at room temperature. They must be sublimated, heated precisely to go from solid directly to gas inside the delivery system. Air Liquide calls this "one of the most impressive technical feats" in advanced materials. Without Mo, 2nm interconnects are uneconomic. Downstream TSMC, Samsung, Intel at 2nm and below. Also 3D NAND >300 layers. Geography US (Entegris, 20+ years in solid precursors, key MoOCl4 patents), France (Air Liquide, new Mo plant in Hwaseong Korea), Germany (Merck).

▸ 8

Substrates & Interposers

mat_substr

HIGH

ABF film (Ajinomoto 90%+ share). Organic laminates (Ibiden, Shinko, Unimicron). Glass substrates emerging (Absolics/SKC, Intel licensing). Silicon interposers for CoWoS.

ABF Substrate Film

Suppliers 1 (Ajinomoto ~95-100%) Scenario ABF insulates the copper wiring layers inside every advanced IC package substrate. It must simultaneously have low signal loss (Dk ~3.1), survive 260C+ solder reflow, bond to copper, and be laser-drillable for microvias. 40 years of amino-acid-derived resin chemistry that nobody else has replicated. A $50-150 ABF substrate enables a $1,000-40,000+ finished accelerator. Market: $4.89B (2025), projected $9.55B by 2033. Substrate makers hold weeks of inventory. Qualification of an alternative would take 2-3 years. Downstream Ibiden, Shinko, Unimicron (substrate makers). Then Apple, NVIDIA, AMD, Intel, every advanced chip package. Geography Japan. Ajinomoto, a food company that invented MSG in 1909, discovered amino acid chemistry made excellent electronic insulation in the 1970s. ABF was perfected in just 4 months in 1996, expected to last 10 years. It is now 25+ years later and still irreplaceable.

▸ 9

HBM Memory Stacks

mat_hbm

HIGH

SK Hynix ~50-80% share (HBM3E). Samsung, Micron ramping. 8-16 die stacks via hybrid bonding + TSV. Critical AI accelerator component.

HBM Memory

Suppliers 3 (SK Hynix ~62%, Samsung ~28%, Micron ~10%) Scenario Samsung failed NVIDIA's HBM3E qualification at least three times in 2025 (overheating). Google reportedly switched from Samsung to Micron. The qualification gauntlet is brutal and there is no shortcut. SK Hynix shipped the first 12-layer HBM4 samples in early 2025. The $54.6B (2026) HBM market is essentially an NVIDIA allocation game. A Korean Peninsula crisis halts 90%+ of HBM, stopping all AI GPU production worldwide. Downstream NVIDIA (directly), AMD, Google, Amazon, Microsoft, Meta. Every AI training cluster and inference deployment on Earth. Geography Korea (SK Hynix + Samsung = ~90%). NVIDIA consumes 60%+ of global HBM output and has pre-allocated 70% of SK Hynix's HBM4 supply for its Rubin platform.

▸ 10

Sub-tier (EUV optics, RF, valves)

mat_subtier

HIGH

EUV laser (TRUMPF), EUV optics (Zeiss), RF generators (MKS, Comet), vacuum valves (VAT 70%+), vacuum pumps (Edwards, Pfeiffer, Osaka Vacuum). Hidden monopolies.

Vacuum Valves

Suppliers 1 (VAT ~76%, ~90%+ at cutting edge) Scenario Every etch chamber, every deposition chamber, every ion implanter at every leading-edge fab uses vacuum valves. They must achieve leakage rates of 10^-9 to 10^-12 mbar*L/s (essentially perfect vacuum), generate near-zero particles during actuation, and survive corrosive gases at extreme temperatures. 50+ years of refinement to tolerances competitors cannot match. EBITDA margins never fall below 30% even in downturns. Existing valves last, but new equipment builds halt without VAT. Downstream Applied Materials, Lam Research, ASML, Tokyo Electron, and every other equipment OEM. Then every fab that needs new tools. Geography Haag, Switzerland (population ~4,700). Founded 1965 by Austrian engineer Siegfried Schertler. IPO only in 2016. $10B+ market cap that most technology analysts have never heard of.

▸ 11

Hafnium & High-k Precursors

mat_hafnium

HIGH

HfO2 is the universal high-k gate dielectric since 45nm (2007). Raw Hf metal: ATI (~45-50%), Framatome (~35-40%) of Western production — duopoly, byproduct of nuclear Zr refining. Global capacity ~140-150 tonnes/yr, ~88t produced (2024). Precursors (TDMAH/TEMAH/HfCl4): Entegris, ADEKA (sole Samsung supplier), Merck (acquired Mecaro MAP Hf), SK Trichem (sole SK Hynix supplier, TCLC JV). TCLC patent expires Nov 2026. Price surged 3-8x since 2022.

Hafnium Metal Supply

Suppliers 2 major Western (ATI ~45-50%, Framatome ~35-40%) Scenario Price surged from $1,566/kg (2020) to $12,508/kg (Mar 2026), a 698% increase in 6 years. Only ~88 tonnes/yr produced because supply is mathematically locked to nuclear zirconium demand. You cannot increase hafnium output without building more nuclear Zr refineries (3-5 years) or increasing reactor construction (decades). Recycling rate: ~1%. A few cents of hafnium per chip enables the HfO2 high-k gate dielectric in every transistor at 45nm and below. There is no substitute. DRAM's shift from ZrO2 to HfO2 capacitors further tightens supply. TCLC patent controlling Korean precursor market expired Nov 2026. Downstream Every advanced logic and DRAM fab on Earth. A hafnium shortage stops all chips at 45nm and below. Geography France (Framatome/CEZUS, Jarrie) + USA (ATI, Albany OR). Byproduct of nuclear Zr refining — ~88 tonnes produced in 2024 vs ~140-150t global capacity. China/Russia produce additional ~15-20t/yr. Supply structurally inelastic. Price surged from ~$1,400/kg (2022) to >$6,000/kg (2024). US Critical Mineral (USGS 2025).

▸ 12

Glass Substrates (emerging)

mat_glass

Absolics (SKC) targeting first mass production 2025 (Georgia fab, CHIPS Act $75M). Intel $1B R&D line, 600+ patents, now licensing. Samsung targeting glass interposers by 2028.

▸ 13

SiC & GaN Materials

mat_sic

HIGH

Wide-bandgap: higher voltage, temp, switching speed. EV inverters, fast chargers, data center power. 6-inch to 8-inch transition. Wolfspeed leads substrates.

SiC Substrates (200mm)

Suppliers 3+ (Wolfspeed ~34%, TanKeBlue ~17%, SICC ~17%, Coherent ~15%) Scenario The most spectacular self-destruction in semiconductors. Wolfspeed's stock fell 96%+ from its 2021 peak. Their 6-inch wafers once sold for $1,500 each. Chinese rivals now offer them for $500 or less. TanKeBlue and SICC captured 17% each in 2024. Renesas reportedly abandoned SiC plans. Wolfspeed emerged from bankruptcy with fabs intact but the market it bet $6.5B on has been commoditized by Chinese competition faster than anyone expected. The 200mm transition remains the bottleneck for power semiconductor scaling. Downstream Infineon, STMicro, ON Semi, Rohm. Cascades to EV inverters, data center power, renewable energy infrastructure. Geography US (Wolfspeed, Coherent) vs China (TanKeBlue, SICC). Wolfspeed filed Chapter 11 Jun 2025 after accumulating $6.4B in liabilities building 200mm SiC fabs. Emerged 91 days later after eliminating $4.6B in debt. Shareholders got 3-5%.

▸ 14

Equipment (scanners, etch, dep)

mat_equip

ASML (lithography), Applied Materials (broadest portfolio), Lam (etch leader), TEL (multi), KLA (inspection). ~$100B annual market.